Experiment 4 - MOS Device Characterization

W.T. Yeung and R.T. Howe

UC Berkeley EE 105

In this experiment, you will find the device parameters for an n-channel MOSFET. From the parameters, you will reproduce its I-V characteristics and compare them to SPICE. The characteristics will be compared to the SPICE level 1 model. We will also compare your data with data from the HP 4145 analyzer. The key concepts you should learn in this lab are:

determining which region of operation the MOSFET is in depending on the values of V_GS and V_DS,

application of correct equations for I_D depending on the region of operation,

extraction of basic SPICE parameters from experimental measurements

1. Background reading: H & S Chapter 4.1 - 4.3, 4.5-4.6.

2. Vladirmirescu - pp. 101-109, pp.126-127. Prepare a SPICE deck for the circuit in Fig. 1. Let V_DS range from 0 - 5V in 0.1V increments and let V_GS range from 0 - 5V in 1V increments. Print a plot of I_D vs. V_DS with V_GS as a parameter. Using this plot, explain how one would obtain the parameters V_TOn, K_n=_nC_ox and _n. Use the following SPICE parameters for getting started: (note SPICE uses K_p for K_n.)

V_TOn =1 V

K_p=550 (A/V²)

_n = 0.05 V^-1

FIGURE 1.

3. Prepare a SPICE deck for the circuit in Fig. 2. Print a plot of I_D vs. V_GS. Let V_GS range from 0 to 5V. Using this plot, explain how one would obtain the parameters V_TO and K_n=_nC_ox. Use the same SPICE parameters as procedure 2.

FIGURE 2.

1. Load the program PIDVD into the 4145 by using the following keystrokes: [GET] PIDVD [EXE]. This program will gather data that corresponds to prelab procedure 2.

2. Place chip Lab Chip 1 into the test fixture and connect the SMUs according to how they are configured in the Channel Definition screen. Pinouts for NMOS1 are as follows: (drain = PIN3 gate = PIN4 source = PIN 5). Set SMU4 to common and connect to pin 14 to provide a ground reference for the chip.

Figure 3 shows how SMUs are connected to the pins of the chip. Figure 4 shows how the SMUs are being used in the experiment.

FIGURE 3.

FIGURE 4.

3. Go to the SOURCE SETUP page using the [NEXT] or [PREV] key and note what voltages/currents are constant and what voltages/currents are variables. Continue to the MEAS & DISP MODE SETUP page and note the settings.

4. Go to the Graphics PLOT page, hit the [SINGLE] key. This will perform the measurement. Hit {AUTO SCALE} to optimize the display of the results. The CRT should look something like figure 5.

FIGURE 5.

1. Toggle through the {EXTN} key until you find the softkey {MARKER}. Hit the {MARKER} key and you will notice a small o.

2. Hit the softkey {MARKER SKIP} twice until you reach the third curve (V_GS=3V). You can move the marker using the cylindrical knob. Notice that as you move the marker along the V_DS axis, the corresponding I_DS value is displayed on the CRT. Move the marker to V_DS = 2V. What is the region of operation of the MOSFET?

3. Fit a line between V_DS = 2V and V_DS = 4V. If you have forgotten how to fit a line, consult the instructions in lab1.

4. Find _n from the slope of the line.

5. Comment on the shape of the graph. In particular, how does V_DS(SAT) compare with theory? How does I_D(SAT) compare with theory? Your comparisons should be quantitative.

FIGURE 6.

6. Obtain a plot of your data by keying in [PLOT] [EXE].

1. Load in the program PV2 with the following keystrokes: [GET] PV2 [EXE].

2. Connect the SMUs according to how they are configured in the Channel Definition screen.

3. Once again, observe the setup in the SOURCE SETUP page and the MEAS & DISP MODE SETUP page.

4. The figure below (Fig. 7) shows the functions of the SMUs. Note that the MOSFET is in the triode region for V_GS > V_TOn + 50 mV; write the equation for I_D that corresponds to this region of operation.

FIGURE 7.

5. Toggle to the Graphics PLOT page and the [SINGLE] key to perform the measurement. Hit {AUTO SCALE} to rescale the curve. From your plot of I_D vs. V_GS in the triode region, find the best-fit line and estimate both V_Tn and the K_n parameter.

6. Obtain a plot of your data by keying in [PLOT] [EXE].

1. Load in the program PV2 with the following keystrokes: [GET] PV2 [EXE].

2. Connect the SMUs according to how they are configured in the Channel Definition screen.

3. Once again, observe the setup in the SOURCE SETUP page and the MEAS & DISP MODE SETUP page.

4. Figure 8 shows the functions of the SMUs. Note that the MOSFET is in the saturation region for V_GS < V_TOn + 5 V; write the equation for I_D that corresponds to this region of operation.

5. Toggle to the Graphics PLOT page and the [SINGLE] key to perform the measurement. Hit {AUTO SCALE} to rescale the curve. From your plot of I_D^1/2 vs. V_GS, find

6. Obtain a plot of your data by keying in [PLOT] [EXE].

7. As you did with the I_D vs. V_DS plot in Section 3.2, find the best fit line for the plot of I_D^1/2 vs. V_GS in the saturation region, as shown in Fig. 10. Use the slope and intercept of the best-fit line to estimate both V_Tn and the K_n parameter.

FIGURE 8.

FIGURE 9.

FIGURE 10.

1. Fill in the value of V_TO, K_n, and _n in the data sheet in the appendix. You will need to refer to these values in future labs.

2. The values you extracted will be used in SPICE to model the NMOS. Using the SPICE decks that you have done for prelab, replace the values of V_To, K_n, and _n with the ones you just found. (note that K_n is defined as K_p in SPICE)

3. Obtain plots of I_D vs. V_DS and I_D vs. V_GS as you did in prelab.

4. Compare the experimental plots with the plots you generated in SPICE. How do the values of I_D(SAT) compare for a given V_DS(SAT)? Note that the level 1 SPICE model is not adequate for accurate modeling of devices with channel lengths shorter than around 2 m.

1. Using the programs PVT and PIDVD, change the settings in the CHANNEL DEFINITION and SOURCE SET UP page to perform the experiments for the PMOS1 device on Lab Chip 2.

These devices consist of stacks of 2 (NMOS2) or 6 (NMOS3) NMOS1 transistors. The effective channel lengths are 3 m and 9 m, respectively. See the Appendix for the circuit schematic and layout of NMOS2 and NMOS3. Perform the same measurements on these devices. Do they better fit the simple Level 1 SPICE model?

Consider the following NMOS:

FIGURE 11.

This long channel MOS transistor is the equivalent of the "stack" shown in figure 11.

FIGURE 12.

It is possible to make a "long" channel device using a series of short channel devices. The effective channel length is the sum of the channel lengths. For the tile array on which these chips were built, there were only the N3515 short channel devices. Hence, the designer chose to put the devices in series to achieve the longer gate lengths. The above MOS composite translates to the following layout design.

FIGURE 13.

Not only can devices be hooked up in series, they can also be hooked up in parallel. We saw in the above example how the length of a device can be increased by arranging the basic transistor in series. The same can be done to the width of the device by arranging them in parallel. This is illustrated in figure 14.

FIGURE 14.

The following layout is one of the transistors which you will be using. Note there are 12 poly gates which are shorted together with metal 1. Note that there is one source that is shared between the two MOSFETs. So there are two MOSFETs which are in parallel. Each of the two MOSFETs in parallel is actually six MOSFETS in series. The drains of the devices are at the left and right end and are shorted together with metal 1. If the width of diffusion area is 46.5 m and each gate has a length of 1.5 m, what is the equivalent W/L ratio for the MOSFET in figure 14.

FIGURE 15.

The equation for the drain current of an NMOS operating in the saturation region is

If we plot the square root of I_D(SAT) vs. (V_GS - V_Tn) for several values of V_SB, we would get a series of straight lines (Here, V_GS is equal to V_DS).

FIGURE 16.

Taking the square root of the equation gives

After normalizing the curve, the x-intercepts will find V_Tn for the given V_SB. For V_SB = 0 V, we find V_Tn = V_TOn.

To find , we note that

By finding the appropriate value of V_SB and V_Tn, we can calculate , since 2|_p| ( 0.6V) is a weak function of the doping concentration.

From the square root of I_D equation, you can tell that K_n is found from the slope of the line. Since C_ox is specified, _n can be found.

Theoretically, once the MOS enters into the saturation region, the drain current should remain constant. The theory presented so far treated the channel length L as being a constant. However, this is not so. The space charge region at the drain junction varies with the drain voltage. This makes L a function of V_DS. As the channel length decreases with increasing V_DS, the drain current increases. This is easily modeled using a parameter _n which is a constant linearly proportional to V_DS. The drain current is then modified to

The value 1/_n is merely the x-intercept of the tangents to the curves of the I_D vs. V_DS plot.

FIGURE 17.

On the above graph, the best thing to do is to find an "average" _n. From the saturation region, find I_D at a given V_DS and another I_D at another V_DS (several volts further along the graph). The inverse of the slope should be the output resistance. Remembering that r_o= 1/(_n I_D), you can calculate using an average I_D. Take several values of _n for different values of V_GS and average them.

Note that the circuit parameters can be obtained from the MOSFET in the linear, or triode region as well.