Experiment 13 - Differential Amplifiers

Y. Shin, J.C. Rudell, W.T. Yeung, R. A. Cortina, and R.T. Howe

UC Berkeley EE 105

In this experiment, we will examine some of the properties of both bipolar and MOS differential gain stages. The lab begins with a procedure for setting the DC bias required to obtain the correct operating point for a differential pair. With the bias conditions set, you will then measure the small signal gain for both a MOS and bipolar "diff. pair" while varying the load resistance. Two-stage differential pairs will also be examined along with other configurations which include an emitter degenerated gain stage and diff. pair commonly used to combat the effect of input offset voltage.

To show your understanding of the lab, your write-up should contain:

2-Port representations of the differential pair

A discussion on the output offset voltage.

A comparison between single-stage amplifiers and differential amplifiers

A discussion on DC biasing issues

A discussion on trade-offs between MOS and BJT differential pairs

H & S: Chapters 11.1 - 11.2

M3501 _F = 104.3 V_An= 43.3V

N3515 V_TOn = 0.88 V _nC_ox=79.47 A/V² _n = 0.06 V^-1

A single BJT differential pair is shown below. For R_L1 and R_L2=1 k, calculate I_BIAS to set V_O1 and V_O2 at a level that will give the maximum output swing. Assume V_CEsat =0.2 V and V_BE = 0.7 V. With your value of I_BIAS calculate the differential mode gain A_dm=v_out/v_{in and the common mode gain Acm=vout/vin.} What is the CMRR?

FIGURE 1.

A single MOS differential pair is shown below. For R_L1 and R_L2=1k, calculate I_BIAS to set V_O1 and V_O2 at 2.75V. Calculate the differential mode gain A_dm=v_out/v_{in and the common mode gain Acm=vout/vin.} What is the CMRR?

FIGURE 2.

1. Connect up the bjt diff. pair circuit shown in figure 3. Use R_L1,2=2.5k and R_BIAS =2 k. Note the collector currents and collector voltages. Also note I_BIAS.

2. Adjust R_p1 and R_p2 until V_BQ1 and V_BQ2 is 1.2V.

3. Make sure that all the transistors are in the forward active region of operation.

4. Connect a voltmeter at V_O1. Adjust R_p2 and observe what happens at V_O1. In particular, note the difference in the base voltages when V_O1 0 and V_O1 = 5V.

5. Readjust R_p1 and R_p2 until V_O1-V_O2 is at a minimum (< 100mV) while making sure that the DC values of V_O1 and V_O2 are approximately at 1.2V.

6. The DC voltage required at the base of Q₁ and Q₂ to make the differential output voltage equal zero is referred to as the input offset voltage. By adjusting R_p1 and R_p2, you have removed the offset voltage at the output of the circuit shown in Figure 3. When designing any type of differential amplifier it is extremely important to minimize this offset which will be amplified if we cascade (pass the signal through a series of gain stages) the signal through more than one amplifying stage. Now measure the input offset voltage of the circuit you have just built, V_os=V_BE1-V_BE2=V_BQ1-V_BQ2 using the digital multi-meter. Later in this lab we will discuss how this offset arises and a technique to minimize the input offset voltage of a differential pair

FIGURE 3.

1. To perform an AC analysis, modify the circuit in figure 3 to the circuit in figure 4. Use the signal generator to apply a small sinusoidal input at v_in at 10kHz. Let C₁ and C₂ be large capacitors (10F). Observe the output waveform using the oscilloscope by connecting v_o1 to Channel 1 and v_o2 to Channel 2. Invert Channel 2 and add both Channels together. What can you say about the phase of the signals at v_o1 and v_o2? Why do we need the 100k resistor in series with the signal source? Also, how much is the signal attenuated between the signal source and the base of Q₁? What is A_dm? What is the relationship between the differential gain and the single-ended gain.

2. Increase the amplitude of v_in until the output begins to "rail out" (clip)-record this range of the input voltage and output voltage.

3. To measure the input resistance, measure the voltage gain v_b1/v_in (The gain at the base of the resistor). Using a resistive divider relationship, find the input resistance of the differential pair (The biasing resistors are part of the input resistance).

4. For A_cm, remove R_B2, R_P2 and C₂.and short the bases of Q₁ and Q₂ together. Apply a small sinusoidal input at v_in and use the oscilloscope to measure A_cm by observing the output waveform at v_o1. What is CMRR for this diff. pair?

FIGURE 4.

4. Use SPICE to confirm your experiment. Use transistor data from previous experiments.

Note: R_p1,2 should both be about 3 k_.

1. A two stage diff. pair is shown in Fig. 5. Let R_BIAS be 2 k. Bias the gates of the first stage (pins 5 and 6) to be 2.5V DC using a resistive divider as you did with the bipolar diff pair.

2. As before, minimize the output offset of the first stage by adjusting the variable resistors. What is the effect of a large offset voltage on the second stage? You can play with the variable resistors and see for yourself.

3. Again, note all the drain and bias currents. Verify that all the devices are in its saturation region.

FIGURE 5.

Note: The second stage doesn't need to be biased. It is biased by the first stage.

1. Repeat the procedures for the ac measurements of the bipolar diff pair. This time, find the gain of the first stage as well as the two-stage composite amplifier.

2. As always use SPICE to verify.

When trying to amplify a voltage signal, we always want to have a high input resistance. One way of increasing the input and output impedance of a bipolar differential pair is to degenerate the emitter of Q₁ and Q₂. On Lab Chip 6 there is a differential pair provided (BJTDPDE) which will allow you to investigate some of the properties of emitter degenerated differential pairs.

1. Connect up the emitter degenerated diff. pair circuit shown in Figure 6. Bias the diff. pair using the same procedure in part 3.1 of the lab. Use R_L1,2=50k. Adjust R_p1 and R_p2 until V_BQ1 and V_BQ2 is 1.6V. Why is 1.6V a good bias voltage for the base of Q₁ & Q₂?

2. Calculate the bias current needed for V_O1 and V_O2 to be equal to 2.75V. Adjust R_BIAS until the current through Q₃ equals I_bias and V_o1 and V_o2 equal 2.75V.

3. Connect a voltmeter between V_O1 and V_O2 and adjust R_p2 until V_O1 - V_O2 is a minimum while making sure that V_O1 and V_O2 are about 2.75V.

4. Now measure the offset voltage V_os=V_BE1 - V_BE2= V_BQ1 - V_BQ2. Notice that the offset voltage is larger than that of the non-degenerate diff. pair with the same load resistance. (why?-explain).

1. Apply a small sinusoidal input at v_in at 10 kHz. Observe the output waveform using the oscilloscope by connecting v_o1 to Channel 1 and v_o2 to Channel 2. Invert Channel 2 and add both Channels together. Measure A_vd, and compare with A_vd of non-degenerate case.

2. For A_vc remove R_B2 and R_P2 and short the bases of Q₁ and Q₂ together. Apply a small sinusoidal input at v_in and use the oscilloscope to measure A_cm by observing the output waveform at v_o1. What is CMRR for this diff. pair? Compare this with that of the non-degenerate case. Use SPICE to calculate A_vd, A_vc and R_in.

FIGURE 6.

Due to a mismatch in the input transistors and in the collector load resistors, there will be always be a slight offset in the output DC level. As explained before, this offset will degrade the maximum output voltage swing and can potentially be amplified by cascaded gain stages. For our differential pair there isn't much we can due to alleviate the problem of the mismatch between load resistors. However, there is a very popular technique for lowering the mismatch between the two input transistors.

During the fabrication of integrated circuits, mismatches between identical transistors, resistors and capacitors are created by process variations across the entire wafer. For example, variations in the value of on-chip capacitors can be attributed to a change in the thickness of the dielectric from one end of the wafer to the other. Process variations can also be the result of a non-uniform implant doping or gas diffusion. The change in process parameters across the wafer usually occur in one direction. Two adjacent devices can still experience a significant mismatch in device parameters even though they are physically close to each other. Fortunately, a technique know as "common-centroid layout" exists to minimize the effect of process variations. When trying to critically match devices as in the input stage of an Operational Amplifier two devices at adjacent angles can be combined to make one device. Figure 7 shows the basic idea of a common-centroid, here we see two devices combined to make one large device. Any process variation in the x or y direction will automatically be cancelled by the two devices.

FIGURE 7.

To exacerbate the effect of mismatch between input devices, we have deliberately laid out a differential pair with input devices on opposite corners of Lab Chip 6 (See Figure 8). Measure the input offset voltage using the procedure in part 3.1 of this lab. Now measure the value of the load resistors. How much of the input referred offset is attributed to the mismatch in the load resistors? How much input referred offset is due to Q₁ and Q₂?

FIGURE 8.

Shown below (Figure 9) is a schematic of an on-chip differential pair with matched input devices using a common-centroid layout. Also shown below in Figure 10, we see the actual layout of the circuit shown in Figure 9. Try to identify and understand this layout, as much as feasible given the black-and-white rendering. Then using the same resistor values as you did for the unmatched diff. pair, again measure the input offset voltage. Is there been a significant improvement in the input referred offset?

FIGURE 9.

FIGURE 10.